The present invention relates to domino logic circuits. More particularly, the present invention relates to a circuit and method of enabling the elimination of the clocked evaluation transistor (footer transistor) in traditional domino logic gates by using clocks with differing duty cycles to control cascaded domino gates.
A typical N-type prior art domino circuit 10 is shown in FIG. 1(a). Domino circuit 10 is made up of three distinct transistor arrangements. First, domino circuit 10 has one or two clocked transistors MNO and MPO. The first clock transistor is P-channel transistor MPO, which is the precharge transistor and its presence is mandatory in every domino circuit. The second clocked transistor is N-channel transistor MNO, which is the evaluation transistor or “footer” transistor and can be omitted from circuit 10 in certain cases, which is described in further detail below. If the footer transistor is present in the domino logic gate, it is known as a “footed” domino gate. If the footer transistor is omitted, it is known as an “unfooted” domino gate. The second element of a domino circuit is the output driver, which includes P-channel transistor MP1 and N-channel transistor MN3 as is shown in FIG. 1(a). The driver is shown as an inverter in the example of FIG. 1(a), but it can be any inverting function (e.g. NOR, or NAND). Finally, domino circuit 10 contains one or more N-channel transistors between node ‘ZA’ and ground (or between node ‘ZA’ and the footer transistor, if one is present). These transistors, which are shown as N-channel transistors MN1 and MN2 in FIG. 1(a), are known as the “pull down stack” (or “pull down network”) and their arrangement determines the logic function realized by domino gate 10. The pull down stack is equivalent to the N-channel pull down stack in traditional static CMOS logic gates. The logic symbol for a domino AND logic gate 12 is shown in FIG. 1(b) corresponding to the circuit 10 shown in FIG. 1(a).
The basic operation of a domino gate consists of two phases. During the first phase, known as the precharge phase, the clock signal is low. Transistor MPO is active and allows node ‘ZA’ to charge to a power supply voltage level ‘VDD’. A direct path to ground, which would prevent node ‘ZA’ from being charged fully is prevented by transistor MNO which is in the cutoff state during precharge. The presence of transistor MNO in circuit 10 guarantees correct operation of the gate independent of the voltage levels on the gates of the transistors MN1 and MN2 in the pull down network. During precharge, the output node ‘Z’ goes low in response to node ‘ZA’ being pulled high. The second phase of a domino circuit's operation is the evaluation phase, which starts when the clock goes high. The internal precharge node ‘ZA’ either remains charged or is discharged through the pull down stack and footer transistor, depending on the voltage levels on the gates of the pull down transistors. Hence, the output node ‘Z’ either remains low or goes high during the evaluation phase.
The purpose of the footer transistor MNO is to ensure that there is no direct path to ground during the time that circuit 10 is precharging (when the clock signal is low). However, the inclusion of a footer transistor is undesirable for three reasons. First, the domino logic circuit slows down due to having an extra series transistor through which node ‘ZA’ must be discharged. The second consequence of using a footer transistor is increased power consumption since the clock tree loading is increased by this transistor. Finally, the area of a footed domino cell may be larger, although layout constraints may dictate the same cell area for both a footed and unfooted version of a given domino gate.
As is known in the prior art, the footer transistor in a domino cell can be eliminated if at least one transistor in every path to ground is turned off at any given time, for the duration of the precharge cycle. If one of the paths to ground is turned on during the precharge cycle, then the cell may never precharge correctly and consequently it may evaluate a wrong value. Alternatively, the precharge time may increase significantly, creating a violation later on in the path. It has been suggested that it is safe to use unfooted domino logic in a configuration in which the inputs to the pull down network may go high during the second half of the precharge cycle. However, this condition causes excessive power to be consumed since there is a direct path from VDD to ground.
When using traditional domino clocking techniques, the conditions to eliminate the footer transistor cannot be guaranteed except in special cases. The footer transistor can be eliminated if the following conditions are met. Multiple overlapping phases must be used to clock the domino circuits and every path to ground must contain at least two transistors, each driven by domino gates that are clocked by a different phase. Specifically, one transistor must be driven by a cell clocked with the same phase that the unfooted cell is on, while the other transistor must be driven by a domino cell clocked by the previous adjacent phase (e.g., an unfooted cell clocked with Φ2 must have inputs driven by clock signals having phases Φ1 and Φ2). This is illustrated in FIGS. 2 and 3. FIG. 2 is a prior art domino logic circuit 20 in which the footer transistor is eliminated, and FIG. 3 is a timing diagram 30 associated with the prior art domino logic circuit shown in FIG. 2. In the example shown in FIG. 2, cascaded domino gates U1, U2, and U3 are shown with gate U1 being clocked by the Φ1 clock signal and gate U2 being clocked by the Φ2 clock signal. This is a typical prior art domino clocking scheme which makes use of overlapping, phase-shifted clocks. The input timing conditions to eliminate the footer transistor in domino gate U2 are satisfied since transistor MN1 is driven by a gate clocked by Φ1 and transistor MN2 is clocked by Φ2, and together these transistor constitute the only path to ground. When gate U1 enters the precharge phase, the input A to transistor MN1 goes low, thus preventing a direct path from VDD to ground when U2 enters the precharge phase. When Φ1 goes high and U1 evaluates, the A input to transistor MN1 goes high. However, the input B at transistor MN2 remains low since it is driven by domino gate U3 which is also clocked by Φ2. Hence, the footer transistor can safely be eliminated for domino circuit U2. While the use of unfooted domino is partially described in the prior art, the analysis does not include all conditions necessary to safely use an unfooted domino logic gate. This is because in every pull down path there must also be a transistor clocked by the same phase as the phase the unfooted domino gate to which it is assigned. As discussed above, if this condition is not satisfied, then when the gates clocked with the earlier phase signal go into evaluation mode, the unfooted gate is still in the precharge mode. Hence, there is a direct path between VDD and ground, which causes excessive power dissipation as well as causing the gate to evaluate during precharge.
What is desired, therefore, is use of unfooted domino logic gates and a corresponding method that does not have the power, speed, and die area penalties associated with prior art footed domino logic techniques.